Field of the Invention
The present invention relates to a filter configuration, in particular, to a filter configuration that is suitable for filtering an output voltage signal of a power factor controller, a method for filtering an analog filter input signal, and a power factor controller.
FIG. 1 shows an exemplary embodiment of a power factor controller according to the prior art. Such a power factor controller has the task of forming a uniform output voltage Uout from an alternating input voltage Uin, in which case the intention is for the output voltage Uout to be kept at least approximately constant both in the event of changes in a load that can be connected to output terminals AK1, AK2 and for AC voltages having different peak values or root-mean-square values. To convert the input voltage Uin into the output voltage Uout, use is made of a step-up switching regulator (boost converter) that is connected downstream of a bridge rectifier and has a series circuit including an inductor L and a switch T in parallel with the bridge rectifier BR and a series circuit including a diode D and a capacitor C in parallel with the switch, it being possible to tap off the output voltage Uout at the capacitor C. With switch T closed, the inductor takes up energy and outputs it through the diode D to the capacitor when switch T has, subsequently, been opened.
The switch T, which is a power transistor, in particular, is driven in clocked fashion by a pulse width modulator PWM, the output voltage Uout or the power consumption of the power factor controller being dependent on the frequency with which the switch is closed and on the switch-on duration for which the switch remains closed.
The power factor controller has both a current regulating circuit for regulating the current consumption from the mains and a voltage regulating circuit for regulating the output voltage Uout. The task of the current regulating circuit is to regulate the current IL through the coil such that the average value of the coil current is proportional to the input voltage Uin, or the magnitude of the input voltage Uin, for the comparison of an instantaneous value of the input voltage Uin and of the coil current IL, the pulse width modulator PWM is fed, from a measuring configuration MA1 through a multiplier, an input voltage signal that is dependent on the input voltage Uin, and a voltage Ui that is present across a current sensing resistor Rs, as current signal.
The task of the voltage regulating circuit is to keep the output voltage Uout constant in the event of fluctuations in a load connected to the output terminals AKI1, AK2 or in the event of a variable input voltage Uin. To that end, a second voltage signal, which is dependent on the output voltage and is formed by a second measuring configuration MA2, is compared with a reference value Vref. The information regarding the deviation of the second voltage signal Vs2 from the reference value is fed to the pulse width modulator PWM by multiplication of the differential signal by the first voltage signal Vs1. The amplitude of the voltage signal Vs fed to the pulse width modulator PWM is, thus, raised or lowered depending on the output voltage Uout.
The signal Vs1 fed to the multiplier MUL for multiplication by the first voltage signal, preferably, changes very slowly in comparison with the period duration of the input voltage. To prevent hum signals that are superposed on the output voltage signal Vs2 from distorting the sinusoidal waveform of the voltage signal Vs, and from thus disturbing the regulation of the output voltage, a low-pass filter is provided in the voltage regulating loop. The low-pass filter is formed by two capacitors Cf1, Cf2 and a resistor, which are connected up to an operational amplifier OP1 that forms the difference between the reference signal Vref and the second voltage signal.
The capacitors and the resistor have to be embodied as external components, that is to say, they cannot be integrated in an integrated circuit, which is how the pulse width modulator PWM is usually embodied. This need for external components increases the costs of the drive circuit of the switch.
The paper: xe2x80x9cEasy Power Factor Corrector Using a DSPxe2x80x9d by Yves De Mari et al., Power Conversion, June 1999 Proceedings, pages 585 to 592, discloses using a digital signal processor (DSP) for filtering a signal dependent on the output voltage in a power factor controller. Such a procedure is expedient if a DSP is present, there is still free computational capacity in the DSP, and there is no need for mains isolation between the DSP and a power section of the power factor controller. Otherwise, the use of a DSP that is used only for filtering the voltage signal is too cost-intensive for most applications.
It is accordingly an object of the invention to provide a filter configuration, a method for filtering an analog filter input signal, and a power factor controller that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that can be realized cost-effectively and without external components and that can be accommodated, in particular, as a constituent part of an integrated circuit in a drive circuit of a power transistor.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a filter configuration for filtering an analog signal, including an analog-to-digital converter unit having an input for receiving an analog filter input signal having a magnitude and an output supplying a pulse signal having a sequence of pulses, a number of the pulses per unit time being dependent on the magnitude of the filter input signal, a counter configuration being connected to the output of the analog-to-digital converter unit and receiving the pulse signal from the analog-to-digital converter unit, the counter configuration having at least one counter supplying a counter reading having a value, and a digital-to-analog converter unit connected to the counter configuration, the counter configuration supplying to the digital-to-analog converter unit in each case once during an evaluation interval the counter reading and forming an analog filter output signal having an amplitude dependent upon the value of the counter reading.
Accordingly, the filter configuration has an analog-to-digital converter unit having an input, to which an analog filter input signal is fed, and having an output, at which a pulse signal is available. In such a case, the pulse signal has a sequence of pulses, the analog-to-digital converter unit being configured such that the number of pulses of the pulse signal per unit time is dependent on the magnitude of the filter input signal. Connected downstream of the analog-to-digital converter unit is a counter configuration, to which the pulse signal is fed and that has at least one counter whose counter reading changes depending on the pulses of the pulse signal. The counter is configured such that, in each case at the end of a periodically recurring sampling interval, the counter reading of the at least one counter is acquired and is available as counter output signal. Connected downstream of the counter configuration is a digital-to-analog converter unit, to which the counter output signal is fed and that provides an analog filter output signal dependent on the value of the counter reading.
Such a filter according to the present invention can be used as a filter in a feedback path of a power factor controller, but it can also be used for filtering arbitrary output signals with long time constants from sensors. In particular, the power factor controller can include input terminals for applying an input voltage, output terminals for providing an output voltage, an inductor having an energy uptake, the inductor connected to at least one of the input terminals, at least one switch connected to the inductor and controlling the energy uptake of the inductor, a drive circuit connected to the switch and driving the switch, a feedback path connected to the output terminals and to the drive circuit and feeding a signal dependent upon the output voltage back to the drive circuit, the signal having a magnitude, the feedback path having the filter configuration according to the present invention.
In accordance with another feature of the invention, at least one counter of the counter configuration is, preferably, configured such that it effects exclusively up-counting or exclusively down-counting. Furthermore, the pulse signal and the duration of the evaluation interval are coordinated with one another such that the counter overflows at least once within an evaluation interval and starts to count anew at an initial value.
In accordance with a further feature of the invention, the at least one counter starts to count at an initial value and has a minimum or maximum counter reading and, upon reaching the minimum or maximum counter reading, the at least one counter starts to count at the initial value again.
Such a digital filter having only an up-counter has an integrating action on the filter input signal, the counter readings remaining the same at the end of the evaluation intervals if a filter input signal is established in the case of which the pulse signal formed by the AD converter unit outputs, within the evaluation interval, a number of pulses corresponding to the maximum counter reading of the counter so that the counter overflows once and, at the end of the evaluation interval, again assumes the counter reading at the end of the previous evaluation interval.
Such a filter can be used as an integrating regulator (I regulator) in the voltage regulating circuit of a power factor controller, in which case the AD converter unit, the counter configuration and the DA converter unit can be realized in an integrated circuit without external components. At the gate level, such a filter can be realized with fewer than 100 gates that can be accommodated in the drive chip of a power transistor.
In accordance with an additional feature of the invention, the AD converter unit may be configured as a conventional voltage-controlled oscillator, as is described, for example, in Tietze, Schenk: xe2x80x9cHalbleiterschaltungs-technikxe2x80x9d [xe2x80x9cSemiconductor circuitryxe2x80x9d], 9th edition, Springer, 1991, page 488 et seq. [page 436 et seq.]. Furthermore, the AD converter unit used may also be a so-called sigma-delta converter, which is described for example in the paper xe2x80x9cDesign of a CMOS Second-Order Sigma-Delta Modulatorxe2x80x9d by Bernhard E. Boser et al., 1988 IEEE Solid State Conference, Digest of Technical Papers, pages 258 to 259.
In accordance with an added feature of the invention, the analog-to-digital converter unit has a signal generator configuration for providing a reference signal rising continuously in sections and a clock generator, the analog-to-digital converter unit compares the reference signal and the analog filter input signal, and the analog-to-digital converter unit supplies the pulse signal as a clock signal at the output dependent upon the comparison of the reference signal and the analog filter input signal.
A conventional digital-to-analog converter may be used as the DA converter unit, in which case, for the use in a power factor controller, a multiplying DA converter is, preferably, used that, in addition to the counter output signal, is fed a further signal, for example, the input voltage signal of the power factor controller. A signal corresponding to the product of the further signal with an analog signal dependent on the counter output signal is present at the output of the multiplying DA converter.
In the filter according to the invention, the filter output signal may have a proportional and an integrating component if the counter configuration has a first counter and a second counter, the counter reading of the second counter, at the beginning of an evaluation interval, being set to the value of the counter reading of the first counter at the end of the previous evaluation interval. The counter reading of the second counter at the end of the evaluation interval is fed to the DA converter unit for the purpose of forming the filter output signal. The counter reading of the first counter at the end of the evaluation interval corresponds to the integrating component of the filter output signal. The difference between the counter reading of the second counter at the end of the evaluation interval and the counter reading at the beginning of the evaluation interval corresponds to the proportional component of the filter output signal.
A filter output signal having an integrating and a proportional component can also be generated by a counter that is set to a stored counter reading at the beginning of an evaluation interval, the stored value corresponding to a counter reading of the counter after a first time interval within the evaluation interval. The counter reading at the end of a second time interval subsequent to the first time interval is used for the formation of the filter output signal by the DA converter.
This counter is incremented at the beginning of the evaluation interval, preferably, during a predetermined time interval according to a clock signal proceeding from the value stored in the register, until it is, subsequently, incremented further during the first and second time intervals according to the pulse signal.
The counter reading determined at the end of the first time interval, which counter reading is stored in the register, forms the integrating component of the filter output signal. The integrating and proportional components of the filter output signal are formed successively in the case of this embodiment of the invention.
In all of the embodiments of the filter according to the invention, the analog-to-digital conversion of the filter input signal is equivalent to a sampling of the filter input signal and effects a filtering out of hum components in the filter input signal.
In accordance with yet another feature of the invention, the digital-to-analog converter unit has an output terminal providing the analog filter output signal, a first series circuit having k resistors and k+1 voltage taps, a voltage dependent on the further signal being present across the first series circuit, at least one second series circuit having first and second connection terminals, m resistors, and m voltage taps, a first switch having a first and second contact pair connecting the first and second connection terminals to two different voltage taps of the k+1 voltage taps of the first series circuit, the first switch being driven dependent upon the output signal of the counter configuration, and a second switch selectively connecting one of the m voltage taps of the second series circuit to the output terminal and provide the analog filter output signal, the second switch being driven dependent upon the output signal of the counter configuration.
In accordance with yet a further feature of the invention, the digital-to-analog converter unit has an output terminal providing the analog filter output signal, a first series circuit having k resistors and k+1 voltage taps, a voltage dependent on the further signal being present across the first series circuit, at least one second series circuit having first and second connection terminals, m resistors, and m voltage taps, a first switch having a first and second contact pair connecting the first and second connection terminals to two different voltage taps of the k+1 voltage taps of the first series circuit, the first switch being driven dependent upon the counter reading of the counter configuration, and a second switch selectively connecting one of the m voltage taps of the second series circuit to the output terminal and provide the analog filter output signal, the second switch being driven dependent upon the counter reading of the counter configuration.
In accordance with yet an added feature of the invention, the resistors of at least one of the first series circuit and the second series circuit are different in each case.
In accordance with yet an additional feature of the invention, the analog-to-digital converter unit has a first and second voltage-controlled oscillator each supplying an output signal or a first and second sigma-delta converter each supplying an output signal, the counter configuration has first and second counters, the output signal of the first voltage-controlled oscillator or the first sigma-delta converter is fed to the first counter, an output signal of the second voltage-controlled oscillator or the second sigma-delta converter is fed to the second counter, and the first and second counters are coupled to set the second counter to a counter reading of the first counter.
With the objects of the invention in view, there is also provided a method for filtering an analog signal. The method provides for a filter input signal to be converted into at least one first pulse signal having a sequence of pulses, the number of pulses per unit time being dependent on the amplitude of the regulating signal. Furthermore, in the method, the counter reading of at least one counter is changed according to pulses of the pulse signal, the at least one counter, preferably, effecting exclusively up-counting or down-counting. The counter reading of the at least one counter is determined in predeterminable evaluation intervals, an analog filter output signal dependent on the counter reading determined subsequently being formed, the amplitude of which filter output signal is dependent on the counter reading.
In accordance with again another mode of the invention, there is provided the step of exclusively effecting up-counting or down-counting with the at least one counter. Upon reaching a minimum or maximum counter reading, the at least one counter starts to count at an initial value again.
In accordance with again a further mode of the invention, there is provided the step of increasing the counter reading with each pulse of the pulse signal.
In accordance with again an added mode of the invention, there are provided the steps of changing the counter reading of the at least one counter dependent upon pulses of a clock signal within a first time interval at a beginning of an evaluation interval and subsequently changing the counter reading dependent upon pulses of the pulse signal within a second and third time interval, storing the counter reading at the end of the second time interval, and setting the counter to the stored counter reading at the beginning of the next evaluation interval.
In accordance with again an additional mode of the invention, there is provided the step of setting the third time interval to be longer than the second time interval.
In accordance with still another mode of the invention, there is provided the step of increasing the counter reading by a fixed value within the first time interval.
In accordance with still a further mode of the invention, there are provided the steps of defining a first lower value and a first upper value, and storing the first lower value or the first upper value at an end of the second time interval if the counter reading lies outside an interval defined by the first lower value and the first upper value.
In accordance with still an added mode of the invention, there are provided the steps of defining a lower limit value and an upper limit value and outputting the counter reading of the at least one counter to form a control signal if the counter reading lies within an interval defined by the lower limit value and the upper limit value.
In accordance with still an additional mode of the invention, there are provided the steps of converting the analog filter input signal into a first pulse signal and a second pulse signal each having pulses, providing the at least one counter as a first counter and a second counter, changing a counter reading of the first counter dependent upon the pulses of the first pulse signal and changing a counter reading of the second counter dependent upon the pulses of the second pulse signal, setting the second counter, at the beginning of an evaluation interval, to the counter reading of the first counter at an end of a previous evaluation interval, and forming the filter output signal utilizing the counter reading of the second counter at an end of an evaluation interval.
In accordance with another mode of the invention, there is provided the step of setting frequencies of the first and second pulse signals to differ for the same filter input signal.
In accordance with a further mode of the invention, there are provided the steps of converting the analog filter input signal into the first pulse signal and a second pulse signal each having frequencies and setting the frequencies of the first and second pulse signals to differ for the same filter input signal.
In accordance with an added mode of the invention, during generation of the filter output signal, there is provided the step of, multiplying the counter reading by an instantaneous value of a further signal.
In accordance with an additional mode of the invention, there is provided the step of multiplying the further signal by a predeterminable factor prior to the multiplication, the factor being dependent upon an average value of the further signal.
In accordance with yet another feature of the invention, there is provided the step of setting the amplitude of the filter output signal to be exponentially dependent on the counter reading at an end of an evaluation interval.
In accordance with a concomitant mode of the invention, there is provided the step of setting the amplitude of the filter output signal to not be linearly dependent upon the counter reading at an end of an evaluation interval.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a filter configuration, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.